1. Technical Field of the Invention
The present invention relates to a sequential comparison-type analog-to-digital converter (SAR ADC: Successive Approximation Register Analog-to-Digital Converter).
2. Related Art
A sequential comparison-type analog-to-digital converter (ADC) mounted on a microcomputer or system LSI, is used from the viewpoint of downsizing and maintaining high precision.
FIG. 1 is a block diagram showing a configuration example of a conventional SAR ADC. FIG. 2 is a diagram for explaining a conversion operation in the SAR ADC.
As shown in FIG. 1, the conventional SAR ADC comprises a comparator 12, a control circuit 13, and a DA converter (digital-to-analog converter) 14. An analog input signal Vin is held temporarily by, for example, a sample-holding (SH) circuit 11 and input to the comparator 12.
It is assumed that the SAR ADC has n-bit (8-bit) resolution and full-scale voltage is VFS as shown in FIG. 2. In the first step, the control circuit 13 outputs a digital signal whose bit value of a first bit (b1) is “1” and whose bit values of second and subsequent bits (b2 to bn) are “0” and the DA converter 14 generates and outputs a reference analog signal Vr of a voltage corresponding to the digital signal. The voltage of the reference analog signal Vr in the first step is VFS/2. The comparator 12 compares the voltage of the analog input signal Vin with the voltage of the reference analog signal Vr and outputs a comparison result. The control circuit 13 decides the bit value of the first bit (b1) based on the comparison result. For example, when Vin is larger than Vr, b1 is decided to be “1” and when Vin is smaller than Vr, b1 is decided to be “0”. In FIG. 2, b1 is “1”. In the following explanation, “the comparator compares” means “the comparator compares voltages” and “the DA converter generates a reference analog signal corresponding to a digital signal” means “the DA converter generates a reference analog signal of a voltage corresponding to a digital signal”.
In the second step, the control circuit 13 outputs a digital signal whose b1 is the value (here, “1”) decided in the first step, whose bit value of the second bit (b2) is “1”, and whose bit values of third and subsequent bits (b3 to bn) are “0” and the DA converter 14 generates and outputs the reference analog signal Vr corresponding to the digital signal. In the example in FIG. 2, the reference analog signal Vr in the second step is 3VFS/4. The comparator 12 compares the analog input signal Vin with the reference analog signal Vr and outputs a comparison result. The control circuit 13 decides the bit value of the second bit (b2) based on the comparison result. For example, when Vin is larger than Vr, b2 is decided to be “1” and when Vin is smaller than Vr, b2 is decided to be “0”. In FIG. 2, b2 is “1”.
Subsequently, the bit values of the third and subsequent bits are decided sequentially so that Vr becomes closer to Vin and when the bit value of the nth bit (here, the eighth bit) is decided, a state is brought about where Vr is closest to Vin, and therefore, the digital signal is output as an AD converted value.
The algorithm to change the width, by which the reference analog signal Vr explained above is changed, so that Vr becomes closer to Vin while reducing the width to ½ the width changed in the previous step is referred to as a binary algorithm.
As described above, in the SAR ADC that utilizes a DA converter, signal processing to calculate a digital value for approximation is performed by a voltage. In a general SAR ADC, the operation speed is restricted by the settling time of the output of the DA converter, and therefore, it is difficult to increase the speed, and if an element with a large drive capacity is used to increase the speed, an increase in power consumption occurs.
F. Kuttner (“A 1.2V 10b 20MS/S Non-Binary Successive Approximation ADC in 0.13 um CMOS” Tech. Digest of ISSCC (February 2002)) and M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske (“A 14b 40MS/s Redundant SAR ADC with 480 MHz Clock in 0.13 um CMOS” Tech. Digest of ISSCC (February 2007)) propose the method in which the cycle time is reduced and the settling error resulting from the comparison in a state where the settling of the output of the DA converter is insufficient is allowed by applying the non-binary algorithm. With this method, although the number of steps becomes larger than when the binary algorithm is applied, the cycle time is reduced, and therefore, the speed can be increased as a whole.
However, with this method, the number of steps is increased, and therefore, if a dynamic comparator is used, the power consumption is increased by an amount corresponding to an increase in the number of steps.
T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, N. Takai (“SAR ADC Algorithm with Redundancy”, IEEE Asia Pacific Conference on Circuits and Systems, Macao, pp. 268-271, December 2008) describes the non-binary (redundant) algorithm in the SAR ADC that uses a DA converter.
On the other hand, in order to solve the problem of the settlement time of the output of the DA converter being long, recently, J. Craninckx and G. Van der Plas (“A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7 mW 9b Charge-Sharing SAR ADC in 90 nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp. 246-247, February 2007) and V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. V. Plas, J. Craninckx (“An 820uW 9b 40MS/s Noise-Tolerant Dynamic-SARADC in 90 nm Digital CMOS”, ISSCC (February 2007)) propose a charge-sharing SAR ADC as an SAR ADC capable of realizing the high-speed operation and low power consumption. In the charge-sharing SAR ADC, signal processing to calculate a digital value for approximation is performed by charges. The configuration and operation of the charge-sharing SAR ADC are explained with reference to drawings.
FIG. 3 is a diagram showing a configuration of a charge-sharing SAR ADC that outputs the voltage of the analog input signal Vin after converting it into an n-bit AD converted digital signal. As shown in FIG. 3, the charge-sharing SAR ADC comprises an input signal capacitor Cs, a plurality of reference capacitor circuits 16-1, . . . , 16-n-1, the comparator 12, and a control circuit 17.
One terminal (input terminal) of the input signal capacitor Cs is connected to the input terminal of the analog input signal Vin via a switch SW1 and the other terminal (reference terminal) is connected to a power source of a reference potential (here, GND).
The reference capacitor circuit 16-1 comprises a reference capacitor C1, a switch SW11 that connects one terminal of the reference capacitor C1 to the power source of a reference voltage Vref, a switch SW12 that connects the other terminal of the reference capacitor C1 to the power source of the reference potential GND, a switch SW13 that connects one terminal of the reference capacitor C1 to the input terminal of the input signal capacitor Cs, a switch SW14 that connects the other terminal of the reference capacitor C1 to the reference terminal (GND) of the input signal capacitor Cs, a switch SW15 that connects the other terminal of the reference capacitor C1 to the input terminal of the input signal capacitor Cs, and a switch SW16 that connects one terminal of the reference capacitor C1 to the reference terminal (GND) of the input signal capacitor Cs. In such a configuration, by bringing SW13 to SW16 into an open state and SW11 and SW12 into a closed state, the reference capacitor C1 is charged to the reference voltage Vref. Further, by bringing SW11, SW12, SW15, and SW16 into the open state and SW13 and SW14 into the closed state, the reference capacitor C1 enters a forward connection state where one terminal of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs and the other terminal is connected to the reference terminal of the input signal capacitor Cs, and by bringing SW11 to SW14 into the open state and SW15 and SW16 into the closed state, the reference capacitor C1 enters a backward connection state where one terminal is connected to the reference terminal of the input signal capacitor Cs and the other terminal to the input terminal of the input signal capacitor Cs.
The other reference capacitor circuits 16-2 to 16-n-1 have the same configuration as that of the reference capacitor circuit 16-1; however, the capacitance values of the reference capacitor C1 and reference capacitors C2 to Cn-1 are different. The capacitance values of the reference capacitors Cn-1 to C1 and the input signal capacitor Cs are set to 1:2:4, . . . , :2n−2:2n−1, that is a ratio of power of 2.
The comparator 12 determines whether the voltage of the input terminal of the input signal capacitor Cs is higher or lower than the reference potential (GND).
Based on the determination result of the comparator 12, the control circuit 17 sequentially connects the reference capacitor circuits 16-1 to 16-n-1 to the input signal capacitor Cs while selecting the connection state so that the voltage of the input terminal of the input signal capacitor Cs becomes closer to the reference potential GND, and calculates an AD converted value corresponding to the voltage of the analog input signal from the connection state of the reference capacitor circuits 16-1 to 16-n-1 when the connection of all the reference capacitor circuits 16-1 to 16-n-1 to the input signal capacitor Cs is completed and the final determination result.
FIG. 4A to FIG. 4F are diagrams explaining the operation of the charge-sharing SAR ADC in FIG. 3. For the sake of simplification of explanation, explanation is given using a case where n=3, i.e., three bits, as an example. Therefore, the two reference capacitor circuits 16-1 and 16-2 are provided, the capacitance values of the reference capacitors C2, C1 and the input signal capacitor Cs are 1:2:4 and these are expressed by C, 2C, 4C. The analog input signal Vin the charge-sharing SAR ADC can convert digitally is in a range between +Vref and −Vref and Vin outside the range is “111” or “000”.
The operation of the charge-sharing SAR ADC is explained with reference to FIG. 4A to FIG. 4F.
First, a sampling step is performed. In the sampling step, as shown in FIG. 4A, SW1 is brought into the closed state and the analog input signal Vin is applied to the input signal capacitor Cs and at the same time, in the reference capacitor circuits 16-1, 16-2, SW11 and SW12 are brought into the closed state, SW1 to SW16 into the open state, and the reference voltage Vref is applied to the reference capacitors C1, C2. After that, SW1 is brought into the open state and the SW11 and SW12 into the open state. Due to this, the input signal capacitor Cs is charged with charges of Qin=4C×Vin and the reference capacitors C1 and C2 are charged with C×Vref and C×Vref.
In a first comparison step, as shown in FIG. 4B, the comparator 12 determines whether the voltage of the input terminal of the input signal capacitor Cs is higher or lower than GND.
In a second comparison step, when the determination result in the first comparison step is “1”, as shown in FIG. 4C, SW15 and SW16 of the reference capacitor circuit 16-1 are brought into the closed state and one of the terminals of the reference capacitor C1 is connected to the reference terminal of the input signal capacitor Cs and the other terminal of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs, i.e., connection is made in the backward connection state. Due to this, the total charges accumulated in the input signal capacitor Cs and the reference capacitor C1 are Qx=4C×Vin−2C×Vref and the voltage of the reference terminal is Vx=Qx/(4C+2C)=(4×Vin−2×Vref)/6. In this state, the comparator 12 makes a comparison.
When the determination result in the first comparison step is “0”, as shown in FIG. 4D, SW13 and SW14 of the reference capacitor circuit 16-1 are brought into the closed state and one of the terminals of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs and the other terminal of the reference capacitor C1 is connected to the reference terminal of the input signal capacitor Cs, i.e., connection is made in the forward connection state. Due to this, the total charges accumulated in the input signal capacitor Cs and the reference capacitor C1 are Qx=4C×Vin+2C×Vref and the voltage of the reference terminal is Vx=Qx/(4C+2C)=(4×Vin+2×Vref)/6. In this state, the comparator 12 makes a comparison.
In a third comparison step, when the determination result in the second comparison step is “1”, as shown in FIG. 4E, SW15 and SW16 of the reference capacitor circuit 16-2 are brought into the closed state and one of the terminals of the reference capacitor C2 is connected to the reference terminal and the other terminal of the reference capacitor C2 is connected to the input terminal of the input signal capacitor Cs, i.e., connection is made in the backward connection state. If the total charges accumulated in the input signal capacitor Cs and the reference capacitor C1 when the second comparison step is performed is assumed to be Qx2, because of the reference capacitor C2, Qx=Qx2−C×Vref and the voltage of the reference terminal is Vx=Qx/(4C+2C+C)=(Qx2−C×Vref)/7. In this state, the comparator 12 makes a comparison.
When the determination result in the second comparison step is “0”, as shown in FIG. 4F, SW13 and SW14 of the reference capacitor circuit 16-2 are brought into the closed state and one of the terminals of the reference capacitor C2 is connected to the input terminal of the input signal capacitor Cs and the other terminal of the reference capacitor C2 is connected to the reference terminal of the input signal capacitor Cs, that is, connection is made in the forward connection state. Due to this, Qx=Qx2+C×Vref and the voltage of the reference terminal is Vx=Qx/(4C+2C+C)=(Qx2+C×Vref)/7. In this state, the comparator 12 makes a comparison.
Explanation is given with a specific voltage value of Vin as an example. FIG. 5 is a diagram explaining an example of a change in a voltage Vx of the input terminal when 0 (GND)<Vin<+Vref/4 and in this case, the correct conversion result is that the digitally converted value is “100”.
At the time of the first comparison step, as shown in (A) of FIG. 5, the charges accumulated in the input signal capacitor Cs are Qx=4C×Vin and the voltage of the reference terminal is Vx=Qx/4C=Vin and 0 (GND)<Vin<+Vref/4, and therefore, the determination result is “1”.
At the time of the second comparison step, as shown in (B) of FIG. 5, Qx=4C×Vin−2C×Vref, Vx=(4×Vref−2×Vref)/6, and 0 (GND)<Vin<+Vref/4, and therefore, the determination result is “0”.
At the time of the third comparison step, as shown in (C) of FIG. 5, Qx=4C×Vin−2C×Vref−C×Vref=(4×Vin−3×Vref), Vx=(4×Vin−3×Vref)/7, and 0 (GND)<Vin<+Vref/4, and therefore, the determination result is “0”.
In this manner, the converted digital value is “100”.
In the above-mentioned charge-sharing SAR ADC, the capacitance values of the reference capacitors Cn-1 to C1 and the input signal capacitor Cs are set to 1:2:4, 2 n−2:2n−1, i.e., a ratio of powers of 2.
In the general SAR ADC, in each step, a comparator with high power consumption and low noise is used. In contrast to this, M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske (“A 14b 40MS/s Redundant SAR ADC with 480 MHz Clock in 0.13 um CMOS” Tech. Digest of ISSCC (February 2007)) proposes to use a comparator with low power consumption and high noise in the first half and a comparator with high power consumption and low noise in the second half in the charge-sharing SAR ADC to further reduce power consumption. In the proposed method, a redundant step of one LSB transition is added to the last of the binary algorithm and at first, a comparator with high noise and low power consumption is used and in the last two steps, a comparator with low noise/high power consumption is used. Then, by correcting the determination error due to the noise of the comparator with high noise in the last two steps in which the comparator with low noise is used, high precision and low power consumption are realized. As a comparator, a dynamic comparator is used. Through the dynamic comparator, no constant current flows, and therefore, power is consumed only by the comparator that operates. Consequently, power consumption can be reduced in the period of time during which the comparator with low power consumption is used in the first half.